1. Field of the Invention
This invention relates to semiconductor fabrication and, more particularly, to a gate conductor with opposed lateral surfaces upon which a spacer is formed having a substantially straight and vertically rising sidewall surface that is less susceptible to accumulation of a silicide-forming metal.
2. Description of Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application. It is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased.
In order to form highly conductive ohmic contacts in the connecting region or "window" between the interconnects, it is oftentimes necessary to incorporate a layer of refractory metal at the window juncture. The refractory metal, when subjected to high enough temperature, reacts with the silicon-based material in the contact window to form what is commonly called a "silicide". The unreacted metal is removed after a low resistivity silicide is at least partially formed. Silicides are well known in the art and provide dependable silicon contact as well as low ohmic resistance.
Self-aligned silicides on source/drain regions, i.e., "salicides", have increased in popularity due to the shrinking dimensions of conventional transistors. As the contact window decreases in size, it is important that contact resistance remain relatively low. Further, aligning contact windows via a separate masking step makes minimizing source/drain regions impossible. For these reasons, salicides remain a mainstay in semiconductor processing because they are good conductors and they are formed using a self-aligned process. When a metal is deposited and heated on a polysilicon gate and a silicon source/drain area, the silicide reaction occurs wherever the metal is in contact with the heavy concentration, silicon-based underlayer. However, as device dimensions shrink, so does the spacing between contact windows. Any silicide forming in light concentration areas or into areas of lateral migration must be carefully monitored and controlled. Otherwise, a phenomenon often referred to as "silicide shorting" can occur.
Silicide shorting often arises when the refractory metal is titanium and when titanium silicide is allowed to form between silicon contact windows, such as between a polysilicon gate and silicon source/drain areas, i.e., junctions. In a lightly doped drain (LDD) process, spacers normally exist on lateral surfaces of the polysilicon to separate the channel from the heavily concentrated source/drain junctions. The spacers are relatively small in size. Spacers are often made from an oxide material, and hereafter are referred to as "oxide spacers". During titanium silicide formation resulting from annealing in an inert-gas atmosphere (e.g., argon) at temperatures above 600.degree. C., silicon diffuses into the titanium and then reacts over the oxide spacer regions. Formation of titanium silicide over the oxide spacer regions provides a capacitive-coupled or fully conductive path between the polysilicon gate conductor and the source/drain junctions.
FIGS. 1, 2 and 3 provide a better understanding of silicide shorting or bridging as it pertains to LDD technology. FIG. 1 is a top plan view of a transistor 10 comprising a gate conductor 12 which is patterned from, e.g., a polycrystalline silicon ("polysilicon") material dielectrically spaced above a substrate containing active and field regions. An active region 14 is shown surrounded by a field region. Active region 14 is adapted to receive dopants which are self-aligned to the sidewall surfaces of gate conductor 12 as well as to the field regions surrounding the active region. The dopants are those which comprise the source/drain dopants as well as the LDD dopants.
FIG. 2 indicates a cross-sectional view along plane 2--2 of FIG. 1. Specifically, transistor 10 of FIG. 1 is shown in cross section having an oxide spacer 16 arranged adjacent sidewall surfaces 18 of gate conductor 12. Spacer 16 extends laterally outward from sidewall surfaces 18 to define a spacer sidewall. Both the gate conductor sidewall 18 and the spacer 16 sidewall provide mask alignment to respective LDD area 20 and source/drain area 22. A channel 24 therefore exists within a silicon-based substrate 24 between the LDD areas 20, whereby areas 20 are doped at a lower concentration and at lesser energies than areas 22.
Substrate 24 and polysilicon 22 contain significant concentrations of silicon which migrate along paths 26 during silicide formation. The migratory avenues 26 occur primarily within a layer of refractory metal 28 deposited across the entire topography. Refractory metal 28 is typically deposited such that it covers the entire exposed topography, even the curved sidewall surface of spacer 16.
FIG. 3 illustrates a heat cycle 30 applied to the metal layer and the various materials upon which the metal layer is placed. Resulting from heat cycle 30, silicon atoms readily migrate along paths 26 shown in FIG. 2 from the silicon-rich source material across the metal layer above spacer 16 to cause bridging of the ensuing silicide 32 at spacer 16.
A popular refractory metal includes titanium which readily accepts silicon atoms derived from silicon sources, such as polysilicon gate 18 and the doped substrate 24. The stochiometric composition of oxide spacer 16 prevents substantial silicon migration through the oxide. However, the layer of titanium metal does provide a migratory avenue especially if the heat cycle is substantial.
Many researchers and manufacturers advocate a multiple step silicide formation process to help address the bridging problem. First, a refractory metal such as titanium is deposited over the entire topography. Next, the metal film is heated to a low temperature in the presence of a nitrogen ambient to form a reacted, relatively high resistance silicide in the contact windows. Next, the unreacted metal is removed using a wet chemical etch (e.g., NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O) thereby leaving reacted metal or metal silicide in the contact windows. Finally, a higher temperature anneal is performed in order to produce a lower resistivity silicide in regions where the metal has previously reacted.
The two-step anneal process is not always successful, especially if the anneal temperature cycles are not carefully monitored and controlled. If the first anneal temperature is too high, then the oxide spacers might be partially consumed and/or silicon atoms might readily migrate into the titanium metal from the substrate or gate conductor causing undesired silicide shorting. Thus, the first anneal temperature must be carefully maintained and is highly dependent on the thickness of titanium across the spacer sidewall. Moreover, extraction of the wafer and the reacted metal silicide in the interim between the two step anneal process may place impurities or native oxides in the contact window above gate conductor 12 and source/drain region 22.
Another technique often used to prevent silicide shorting is the introduction of nitrogen during one or both anneal cycles. Nitrogen present during the first anneal step will diffuse into the titanium metal and effectively nitrate the upper surface of the metal during the same time in which the lower surface is attempted to form silicide. It is possible that the anneal temperature can be excessive and nitrogen incorporation (i.e., nitridation) can be minimal. Absent nitrogen atoms, which are used to compete with the titanium-silicide bonds formed in the silicide, extensive salicidation can occur making it difficult to remove the metal silicide from the spacer subsequent to the first anneal step.
Not only it is important to carefully control the amount of salicidation as well as nitridation, and to strike a balance between the two during the first and second anneal steps, but is also important to minimize exposure of the refractory metal to oxygen and contaminants during silicide formation. Contaminants can form between the time in which the wafer is removed from the first anneal chamber and exposed to an atmospheric environment prior to insertion into an etch chamber. Additional contaminants can occur within the etch chamber or via the etchant composition itself.
It is therefore desirable that a semiconductor fabrication process be developed which need not be concerned with placing careful controls on salicidation relative to nitridation. More specifically, a desirous process is needed whereby titanium is absent from the spacer sidewall surface altogether. Absent titanium in this critical area, silicide shorting or bridging is not present. Substantially minimizing, if not eliminating, titanium from the sidewall spacer will lessen the concerns of selecting proper anneal temperatures, two-step anneal cycles and contamination induced therefrom.